The invention relates to an improved processor for a programmable controller of the type used to control an industrial machine or process through input and output devices.
In Brown et al, U.S. Pat. No. 4,282,584, issued Aug. 4, 1981, a processor module executes user control instructions by translating and mappping these instructions to respective interpreter routines stored in a programmable read-only memory (PROM) on the module. This allows personnel who use the equipment to enter a program in ladder diagram format, which is easier to understand and represents a higher level language than the assembly language used in designing interpreter routines. This assembly language has been designed by the manufacturer of the particular microprocessor chip that is selected for the prime controlling element in the processor module.
In equipment of this type, an important feature is the speed or rate at which user instructions are executed, because this determines the scan rate at which the status of input devices is sensed and the status of output devices is set. As explained in the above patent application, each interpreter routine has a first portion to execute a control operation and a second portion, referred to as a "fetch" sequence, which is executed to find the first instruction in the interpreter routine for the next user macroinstruction in the control program. This "fetch" routine is thus repeatedly executed, and the quicker the microprocessor can execute this fetch sequence, the faster the user instructions can be executed.
Microprocessor chips typically have a number of internal registers. Some of these are used for pointing to the location of the machine language instructions to be executed by the microprocessor. Typically, a 16-bit word of information in a program counter (PC) register points to the instruction being executed, while a last-in-first-out (LIFO) internal memory area called a "stack" stores the addresses of instructions in subroutines to be executed later. A sixteen-bit register called a stack pointer (SP) is provided to address the stack when "pushing" data onto the stack or "popping" data off the stack. Other internal working registers in a microprocessor are used for storing intermediate data results or as counters.
In the above-mentioned processor module, the operation code and operand address are read out of the main memory and through the translator memory to a pair of internal working registers in the microprocessor. From there the operand address is shifted to another 8-bit working register. The 8-bit operation code becomes the low byte in the 16-bit program counter (PC) register after execution of several register exchange instructions. As the last step in this sequence, the microprocessor executes a jump indirectly to the interpreter routine, which has its address stored in a jump table at the location corresponding to the 8-bit address provided by the operation code. If this sequence could be shortened, the total scan time for a control program of many user instructions would be considerably shortened.
Besides executing each user program instruction with fewer machine language instructions, the execution time for the control program can be decreased by lowering the execution time for each "rung" of the control program. In the industrial control field, the control program usually takes the form of a ladder diagram in which the user program instructions are strung together to form rungs. If the execution of user program instructions produces a sequence of "true" results from one end of the rung to the other, the rung status is also "true." If this string of "true" results is broken by a "false" result, the status of the rung is usually "false," although a rung with multiple parallel branches requires "false" results in each parallel branch before the rung is declared to be "false." In prior controllers, all user program instructions in a rung were executed even after one or more "false" results were encountered. This was not an efficient use of processor time.
Besides increasing the speed of processor operation, it is also desirable to provide security for the control program once it is established, to prevent its loss during power interruption or other conditions that could affect the volatile main memory. To accomplish this, a processor module has been provided with a non-volatile, read-mostly memory into which a master copy of the control program can be transferred upon a user command, and later automatically called up if the program in the main memory cannot be verified. Such a module is disclosed in Ecker et al, U.S. Pat. No. 4,291,388, issued Sept. 22, 1981. In this application, the processor module is part of a programmable interface (PI) in a numerical control system having a relatively large power supply. This PI processor module receives .+-.15 d-c volt signals from the power supply through the backplane and includes circuitry for adjusting these signals to the level necessary to erase the contents of the non-volatile memory and to write control program instructions into this memory.